1. Field
Example embodiments relate to memory devices having characteristics of volatile memory (e.g., dynamic random access memory (DRAM)) and non-volatile memory (e.g., flash memory) and methods of operating the same. More particularly, example embodiments relate to memory cells having volatile and nonvolatile characteristics and multi-bit methods of operating the same.
2. Description of the Related Art
Semiconductor devices include non-volatile memory devices, such as flash memory, and volatile memory devices, such as dynamic random access memory (DRAM). A flash memory may maintain data stored in a memory cell when power is turned off. However, because of the time required to repeatedly write and/or erase data in a memory cell of a flash, a flash memory may not be suitable for frequently rewriting data. The number of times writing and/or erasing data may be repeated may be limited when using a flash memory.
A DRAM may not maintain data stored in a memory cell when power is turned off. Data stored in each memory cell of a DRAM may require steps to periodically refresh the DRAM in order to maintain a data state. However, because repeatedly writing or erasing data in the memory cell of the DRAM takes little and/or decreased time, there may be no limit to the number of times the operation of writing or erasing data can be repeated in the DRAM.
DRAM memory cells are becoming gradually smaller as memory devices are produced with increased storage capacity within a limited area (e.g., increased integration density). A one-transistor (1T) DRAM including a single transistor without a capacitor in a memory cell thereof improves integration density over memory cells requiring a transistor and a capacitor. The 1T DRAM may write data by trapping charges in a floating body or removing charges from a floating body, and may sense data by detecting a difference between threshold voltages of the transistor caused by the trapped charges.
Although integration density is improved by using 1T DRAM technology, limitations in reducing the size of a 1T DRAM cell exist. Further, the number of cells included in a DRAM increases as DRAM capacity is increased, resulting in large sized DRAMs. A memory device having a multi-bit cell capable of storing two or more data states using one cell and a method of operating the memory device may improve integration density.